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This paper presents an efficient fabrication process of highly aligned P(VDF-TrFE) nanofibers based on conventional far-field electrospinning (CFES) technique. By attaching a comb-shape electrode onto a fast rotating drum, the process combines the advantages of plane electrode and rotating-drum-collecting methods, which leads to the orientation of the deposited nanofibers and enhances it. Additionally,...
Portable consumer electronics have a tremendous demand of miniaturization, high density and high performance. 3D SIP is an efficient solution to meet this requirement. This paper had presented an innovative 3D package product configured with stacked die and cavity-embedded substrate. Through hole via in the substrate provides the signal communication at a cost-effective way. This structure satisfies...
The mania for mobility applications such as smart-phones, tablet PCs, and personal computers is sweeping all over the globe. In order to insure the performance of a new product, the Design for Manufacture (DFM) plays an important role on a package design both in research stage and mass product stage. The substrate process capabilities, assembly process capabilities, material properties, and package...
This paper describes a parallel test method based on a cross-point switch which can be programmed to control signal path and the number of switches to be opened according to the number of channels to be tested. In this method, at the transmitting side, one source inputted cross-point switch can be fan-out to multi sources to activate device under test, and different signal trace or length of cables...
Crosstalk noise has become a major performance inhibitor in high speed digital system. This is especially the case in package designs, connector assemblies and circuit interconnects designs. With the simultaneous miniaturization of electronic systems and decreasing signal rise time, it is important to be able to predict major sources of crosstalk and to stay within the cross-talk budget for high-speed...
Differential interconnect lines in multi-gigabits system in package (SiP) packaging system are studied in this paper. The performance of interconnect lines can be easily estimated with jitter and eye opening using the eye diagram that is very helpful metric. To maintain good eye-diagram with high voltage swing and low timing jitter, a signal integrity (SI) design flow of SiP is proposed based on eye-diagram...
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