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A low-power configurable design for an asynchronous SAR ADC that is suitable for analog front-end of sensor ASICs is presented. The proposed architecture employs a majority vote based comparator capable of providing programmable noise performance. The proposed asynchronous digital logic determines the majority vote by employing two counters at the comparator differential output. Simulation result...
Comparator power consumption is a major bottleneck to the power efficiency of a high resolution successive approximation register (SAR) analog-to-digital converter (ADC) used in low-power applications. This paper analyzes theoretically the optimal comparators that need to be used to achieve a desired overall performance at minimum power levels. A simple and accurate mathematical model of the SAR ADC...
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