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In this paper the design of a 10b 100-MS/s pipeline analog-to-digital converter (ADC) with an optimized bit-stage resolution is presented. A careful analysis of the ADC architecture is presented. The proposed architecture is made by two main stages with opamp-sharing technique and a 3b full-flash ADC. The 1st stage has a 1.5b resolution architecture, the remaining stages have 2.5 b resolution architecture...
In this paper the design of the analog baseband chain for UWB receivers in a standard 90 nm CMOS technology is presented. The baseband chain is composed by the 5th order elliptic analog low-pass filter and a programmable gain amplifier (with up to 60 dB gain). Due to the large UWB signal bandwidth (250 MHz), the design has been carried-out using a MATLAB model taking into account the capacitance parasitics...
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