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A 40 GHz phase-locked loop (PLL) with an optimized shunt-peaked buffer is realized in Global Foundries 65 nm CMOS technology. The shunt-peaked buffer placed in the loop eliminates the capacitive loading of the frequency divider and enhances the drive capability. Hence it is possible to use an inductorless frequency divider to reduce potential parasitics in the layout. Thanks to the simplified topology...
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