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Except for regular arrays, yield enhancement for high performance VLSI systems is usually addressed at the physical layers rather than at the architectural level. In addition, pipelines are prevalent in many SoC architectures. In this paper we present new architectural approaches and results to improve the yield and yield/area of pipelines by using redundancy and steering logic . We present a procedure...
There are two strategies for deadlock handling in routing algorithms in NoC: deadlock avoidance and deadlock recovery. Some deadlock recovery routing algorithms are re-injection based, such as: Compressionless (CR), Software-Based (SW_TFAR) and AFBAR. In spite of the performance comparison, none of existing researches have focused on the energy consumption of various routing algorithms. We evaluate...
Asynchronous circuits have many advantages vs synchronous design styles like high performance and lower power consumption; however, there is a drawback of big overhead in handshake circuitry of these circuits. In this paper, we have reduced the amount of these extra circuits by take advantage of some compiler techniques. The compiler methods can be used innovatively to improve the synthesis results...
The rule based scheduling algorithms are a new trend in grid scheduling algorithms; the combination of rule based algorithms for resource selection with various dispatching rules for queuing of jobs can improve or deteriorate their performance. Thus, choosing a proper queuing strategy for each algorithm is a prominent issue in scheduling. In this paper, we introduce two new dispatching rules for resource...
Grid scheduling problems are dynamic as the jobs and resources in the system vary overtime. The Rule-based scheduling algorithms are a new trend in grid scheduling which are applicable in dynamic grid environments; The arriving jobs waiting for execution is ordered according to a certain rule and they are dispatched for processing according to that order. Grid scheduling algorithms usually involve...
Network-on-chip (NoC) is a precious approach to handle huge number of transistors by virtue of technology scaling to lower than 50 nm. Virtual channels have been introduced in order to improve the performance according to a timing multiplexing concept in each physical channel. The incremental effect of virtual channels on power consumption has been shown in literatures. The issue of power saving has...
Deadlock management has a direct effect on making a reliable connection between processing nodes in parallel computers. Networks using wormhole switching are the most vulnerable networks to deadlock occurrence due to chained blocking nature of this switching method. Different hardware based techniques for deadlock recovery were proposed in the literature which have considerable design complexity,...
Traffic models exert different message flows in a network and have a considerable effect on power consumption through different applications. So a good power analysis should consider traffic models. In this paper we present power and throughput models in terms of traffic rate parameters for the most popular traffic models, i e. Uniform, local, HotSpot and First Matrix Transpose (FMT) as a permutational...
Asynchronous microprocessors are more flexible to adapt to physical parameters, and have lower power consumption than synchronous microprocessors. In this paper we will introduce the design of an asynchronous microprocessor (V8-uRISC) and explore its design process compared to synchronous design. The processor is synthesized by Persia, an automatic tool for synthesizing asynchronous circuits. We have...
Technology scaling increases clock rates and die sizes; therefore, power dissipation is predicted to soon become the key limiting factor on the performance of single-chip designs. NoC as an efficient and scalable on-chip communication architecture for SoC architectures, enables integration of a large number of computational and storage blocks on a single chip. Since different applications impose different...
In this paper we analyses the energy consumption of well known family of asynchronous circuits and present a new methodology for energy estimation of these circuits at intermediate-level of abstraction. Energy estimation is performed by simulating the intermediate format of the design. The number of Read and Write accesses on the ports of the concurrent processes are counted by analyzing the conditional...
NoC is an efficient on-chip communication architecture for SoC architectures. It enables integration of a large number of computational and storage blocks on a single chip. NoCs have tackled the SoCs disadvantages and are scalable. In this paper, we compare two popular NoC topologies, i.e., mesh and torus, in terms of different figures of merit e.g., latency, power consumption, and power/throughput...
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