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A 48 channel, 40-65 MS/sec, 10 bit pulse shape digitizer card has been designed in the VME-6U form factor. The design uses 6 octal flash analog to digital converter (FADC) chips (ADS5121 or ADS5122) from Texas Instruments. The FADCs are read out by 6 Altera Cyclone FPGAs. A 7th FPGA is used to collect and merge the event fragments. The present firmware includes trigger latency buffers, waveform segment...
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