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An LC-VCO-based MDLL is presented in a fractional-N frequency synthesizer to extend its frequency multiplication factor and performance. By employing the proposed MUXs in the LC-VCO, it increases the loop bandwidth (BW) from 3MHz to 15MHz (nearly 0.4fREF) as well as flicker noise suppression. Moreover, the re-quantized delta-sigma modulator (DSM) is combined with the prototype in order to reduce spurious...
An ADC-based digital phase-locked loop (DPLL) assisted by a digital-to-time converter (DTC) is proposed for fractional-$N$ frequency synthesis. A successive approximation register (SAR) ADC is adopted to mimic the operation of the time-to-digital converter (TDC) in the conventional DPLL to achieve an equivalent 1-ps time-domain resolution. The superiority of ADC-based TDC is revealed and compared...
A fractional-N PLL employing a dual-frequency clock generator is proposed to achieve lowering the in-band phase noise. The architecture enables the PFD/CP to operate in the linear region to avoid noise-folding effect. An optimum operating condition can be tuned to achieve the best in-band phase noise. The proposed techniques are employed in a 800-MHz fractional-N PLL fabricated in a 0.18-μm CMOS process...
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