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A 10-bit pipelined ADC employs both opamp-and time-sharing techniques to reduce the power consumption and silicon area. The proposed ADC needs only one opamp to complete the 10-bit conversion. This ADC has been fabricated in a 90-nm digital CMOS technology and occupies only 0.058 mm2. It operates at 100 MS/s and achieves an SNDR of 55.0 dB while the power consumption is 4.5 mW from a 1.0-V supply.
A digital calibration technique based on the split-ADC is proposed to correct linear gain errors in a 10-bit pipelined A/D converter, which allows the use of low-gain amplifiers in conversion stages. Fabricated in a 0.35-μm CMOS technology, the core area of the ADC occupies 1.64 mm2. The opamp-sharing technique helps to reduce the core power consumption to 45 mW from a 3-V supply voltage at 50 MS/s...
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