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A 6-bit 800-MS/s pipelined A/D converter (ADC) achieves SNDR and SFDR of 33.7 dB and 47.5 dB, respectively. Employing voltage-mode open-loop amplifiers in gain stages, global gain control techniques, and two-bank-interleaved architecture, the proposed pipelined A/D converter relaxes stringent design tradeoffs between speed and power. Fabricated in a 0.18-mum CMOS technology, the ADC consumes 105 mW...
A 6-b 1.3-Gs/s pipelined successive-approximation analog-to-digital converter (ADC) is presented. Employing improved-MMS and C-2C architecture, the circuit operates in high speed and low power consumption. With open-loop architecture, the T/H circuit can work at a high conversion rate. The proposed architecture reduces the static power consumption by charge redistribution digital-to-analog converter...
A 6-bit 800-MS/s pipelined A/D converter (ADC) with voltage-mode open-loop amplifiers achieves SNDR and SFDR of 33.7 dB and 47.5 dB, respectively. Fabricated in a 0.18mum CMOS technology, the ADC consumes 105 mW from a 1.8-V power supply while the active area is only 0.5-mm2
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