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A FPGA-under-test has to be configured before it is tested. However, traditional configuration for a FPGA-under-test is time consuming due to the fact that the configuration has to be conducted manually many times until each resource of FPGA is not left behind. Automatic configuration generation for a FPGA-under-test implemented by an in-house SOC co-verification technology based FPGA functional test...
HW/SW co-emulation technique combing software simulation with hardware acceleration is one of the popular techniques for SOC verification, where interrupt-based communication mechanism is usually utilized. However, communication overhead will be resulted from data exchange between hardware side and software side at every cycle. A stream-mode based HW/SW co-emulation technique is proposed and presented...
Field programmable gate arrays (FPGAs) have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/software (HW/SW) co- verification technique for FPGA test is proposed and presented in the paper. Taking advantage of flexibility and observability of software in conjunction with high-speed...
Full coverage detection of faults is required for FPGA manufacturing testing. Many researches for FPGA test only focus on algorithms of reduction configuration numbers for a configurable logic blocks (CLB), or interconnect routings without application for manufacturing testing. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, SoC...
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