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We have designed an SoC platform with a multi-channel bus architecture which can reduce the bottleneck of on-chip communication by multi-channels. The platform consists of OpenRISC 1200 processor, WISHBONE crossbar on-chip bus, memory interface, VGA controller, DMA, AC97 controller, debug interface and UART. The crossbar on-chip bus supports up to 8 masters and 16 slaves, WISHBONE compatible peripheral...
We propose a multimedia SoC platform with a crossbar on-chip bus which can reduce the bottleneck of on-chip communication by multi-channels. The platform consists of RISC processor, WISHBONE crossbar on-chip bus, memory interface, VGA controller, DMA, AC97 controller, debug interface and UART. The crossbar on-chip bus supports up to 8 masters and 16 slaves, WISHBONE compatible peripheral IPs and allows...
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