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Effects of electro-less Ni layer as barrier/seed layers were evaluated for high reliable and low cost Cu TSVs. To electrically characterize the effectiveness of a Ni layer as barrier/seed layers for TSV application, we fabricated the trench MOS capacitor with 5µm dia. and 50µm depth TSV array. Via holes were successfully filled by Cu electro-plating by using Ni seed layer. To characterize the blocking...
The influence of Cu contamination from Cu through-silicon via (TSV) on device reliability in the 3-D LSI was electrically evaluated by capacitance-time (C-t) measurement. The Cu/Ta gate trench capacitors with two types of Ta barrier layers of 10-nm and 100-nm thicknesses (at the surface) were fabricated. The C-t curves of the trench capacitors with 10-nm thick Ta layer were severely degraded even...
High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chemical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep...
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