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Memory access latency has a significant impact on application performance. Unfortunately, the random access latency of DRAM has been scaling relatively slowly, and often directly affects the critical path of execution, especially for applications with insufficient locality or memory-level parallelism. The existing low-latency DRAM organizations either incur significant area overhead or burden the...
Automatic parallelization has shown promise in producing scalable multi-threaded programs for multi-core architectures. Most existing automatic techniques parallelize independent loops and insert global synchronization between loop invocations. For programs with many loop invocations, frequent synchronization often becomes the performance bottleneck. Some techniques exploit cross-invocation parallelism...
This paper presents bootloader and debugger architectures that are designed for an NoC-based Multiprocessor System On-Chip (MPSoC). An MPSoC demands scalable bootloader and debugger architectures, especially with the increasing of the number of the processor cores. The proposed bootloader and debugger designs utilize the NoC interconnect network to distribute data to and from the cores. With this...
Sofware-Defined Radio (SDR) has been proposed as a solution for a single device to overcome various and changing radio standards. It allows wide range of computational device, such as personal computer processor and Multi-Processor System-on-Chip (MPSoC) to function as radio baseband processor. Number of works of SDR implementation on MPSoC has been done, variously differing according to underlying...
Today’s mobile consumer electronics devices, such as smartphones and tablets, are required to execute a wide variety of applications efficiently. To this end modern application processors integrate both general-purpose CPU cores and specialized accelerators. Energy efficiency is the primary design goal for those processors, which has recently rekindled interest in neural network accelerators. Neural...
Distributed in-memory key-value stores (KVSs), such as memcached, have become a critical data serving layer in modern Internet-oriented datacenter infrastructure. Their performance and efficiency directly affect the QoS of web services and the efficiency of datacenters. Traditionally, these systems have had significant overheads from inefficient network processing, OS kernel involvement, and concurrency...
While clusters of commodity servers and switches are the most popular form of large-scale parallel computers, many programs are not easily parallelized for execution upon them. In particular, high inter-node communication cost and lack of globally shared memory appear to make clusters suitable only for server applications with abundant task-level parallelism and scientific applications with regular...
A platform that supported sequential consistency (SC) for all codes - not only the well-synchronized ones - would simplify the task of programmers. Recently, several hardware architectures that support high-performance SC by committing groups of instructions at a time have been proposed. However, for a platform to support SC, it is insufficient that the hardware does; the compiler has to support SC...
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