The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, we have explored the design features of a Double-Pole Four-Throw (DP4T) RF CMOS switch with use of a novel Vertical Slit Field Effect Transistor (VSFET). This proposed switch circuit uses the double-gate which minimizes the number of transistors and increases the logic density of the transistor per unit area as compare to simple switch. These double gates are independently controlled...
In this paper, we have discussed the attenuation with ON resistance, isolation and switching speed of a Double-Pole Four-Throw (DP4T) RF CMOS switch, with properties of symmetric double-gate (DG) MOSFET to make obvious the advantages for DG circuits and reduce the number of transistors which increases the circuit density per unit area in addition to functionality as compare to simple CMOS switch....
Elimination of the p-MOS transistor from the pass gate network significantly reduces the parasitic capacitances associated with each node in the circuit, thus, the operation speed is typically higher as compared to the CMOS counterpart. But then the improvement in the transient characteristics comes at the price of increased process complexity. In Complementary pass transistor logic (CPL) circuit,...
Parasitic components of a MOSFET are mainly responsible for the intrinsic delay of logic gates, and they can be modelled with fairly high accuracy for gate delay estimation. The extraction of transistor parasitic from physical structure (mask layout) is also fairly straight forward. The first component of capacitive parasitic, we will examine is the MOSFET capacitances. The classical approach for...
To avoid the uses of multiple RF chain associated with the multiple antennas, RF switch is most essential component. Multiple antennas systems are used to replace traditional single antennas circuitry in the radio transceiver system in order to improve the transmission capability and reliability. The desired switching system must have low cost and simple structure, yet still can capture all the advantage...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.