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A 1-Mb CMOS EEPROM (electrically erasable and programmable read-only memory) using a 1.0- mu m triple-polysilicon, double-metal process is described. To achieve a manufacturable 120-ns 1-Mb EEPROM with a small chip, a memory cell with high current drive, improved differential sensing technique, and error-correcting code (ECC) was developed. The cell size is 3.8 mu m*8 mu m, and the chip is 7.73 mm*11...
A high-performance CMOS technology and cell structure for a megabit EEPROM are described. A novel EEPROM (electrically erasable programmable read-only memory) cell called a stacked floating gate with self-aligned tunnel region (SSTR) cell has been developed. A merged signal transistor structure has been developed to reduce the cell size. A sufficient cell threshold window is obtained in 2 ms at 16...
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