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This brief paper deals with using the particle swarm optimization metaheuristic for optimally sizing switched current (SI) memory cells, namely the class AB grounded gate SI memory cell. Pareto front is generated while optimizing two main conflicting performances: maximizing both the signal to noise ratio and the sampling frequency. SPICE simulation results are presented to validate obtained sizing.
This paper presents the design of an integrated inductor with AMS CMOS 0.35 mum technology. This inductor is designed to ensure the wide band LNA circuit implementation on silicon. This inductor is designed with a coplanar transmission line. This line type achieves an inductance value of 0.38 nH on the whole operating frequency band from 2 to 6 GHz.
Advances in micromachining technology can facilitate the integration of SAW (Surface Acoustic Wave) devices and CMOS circuitry on IC scale substrate for Monolithic fabrication. The optimal design and performance of these filters can be reached by using new Smart materials. The key component in the structure of the SAW device is the piezoelectric materials used which depends mainly on some important...
We present results on optical, structural and electrical properties of a-Si 1−x C x :H films deposited by plasma enhanced chemical vapor deposition in the low power regime, with C fraction from 0 to 0.28. The absorption coefficient has been obtained in the region 0.73–4.5eV by means of ellipsometry, reflectance–transmittance and photothermal deflection spectroscopy. The addition of...
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