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In an era of multi-core and even many-core processors, with the increase of the number of cores integrated on a single-chip, how to organize these cores efficiently is becoming the key issue to make multi-processor systems optimal. The infrastructure of cluster-based multi-processor system-on-chip (MPSoC) is promising, and welcomed because of its hierarchy and scalability. However, how to configure...
A dynamically reconfigurable computing system based on network-on-chip (DReNoC) is proposed, which consists of computing nodes and communication nodes. The computing node is a complete coarse-grained dynamically reconfigurable SoC named DReSoC. And the DReSoCs communicate with each other through on chip network routers. The proposed DReNoC has been implemented on the ALTERA STRATIX II EP2S180 DSP...
While the computational core is becoming faster and faster, the communication efficiency between the processors has become a bottleneck which limits the performance of multiprocessor system-on-chip (MPSoC). This paper focuses on design and implementation of AXI bus protocol-based MPSoC architecture. Firstly, the RTL models of 4 NIOS II processors using AXI communication architecture are developed...
Performance evaluation for Network on Chip (NoC) is still a challenging problem. This paper presents the design of an on-line configurable traffic generator (OCTG) that provides a fast and effective traffic generation environment for evaluating the communication performance of Network-on-Chip (NoC). The novelty of the proposed OCTG architecture lies in the fact that it is different from just having...
The Multiprocessor System-on-Chip (MPSoC) is a promising solution for future complex computer and embedded systems. And, the Network-on-Chip (NoC) has been proposed as the future on-chip interconnection. Whereas, the NoCs bring more challenge on parallel programming and synchronization of different processor cores. This paper proposes a new cluster-based homogeneous MPSoC architecture, which adopts...
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