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This paper presents a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX), which is capable of processing signals with data rates between 107 Gbit/s and 112 Gbit/s. The fabrication of the integrated circuit (IC) relies on an in-house InP double heterostructure bipolar transistor technology (DHBT) featuring cut-off frequency values of more than 350 GHz for...
Broadcasting of digital video signals uses large spectral area. In order to reduce the cost, broadcasters are optimizing their radio network. They build single frequency network (SFN). To maintain efficient quality of service (QoS) to the end user, accurate time synchronization and frequency syntonization is needed between transmitter sites. This function is now fulfilled with local GPS slaved clocks...
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