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This paper demonstrates for the first time a low cost, low complexity process CMOS Hk/MG for low-power applications with Vth controlled by gate Ion-Implantation (I/I) and High-k capping for NMOS and PMOS, respectively. Novel advanced electrical and physical characterizations provide unique insights about the underlying mechanism of Vth adjust induced by I/I into the metal. Improved RO performance,...
We report low Vt (Vt,Lg=1μm=±0.26V) high performance CMOS devices with ultra-scaled Tinv down to Tinv~8Å using a gate-first dual Si/SiGe channel low-complexity integration approach. Compared to a dual dielectric cap gate-first integration scheme, the devices fabricated with the novel scheme show for the same high-k/metal gate stack (1) 3Å reduction in nMOS and pMOS Tinv (2) 220mV lower long channel...
In this paper, we have done a comprehensive study of the junction anneal strategy (by spike and/or laser) for advanced technology nodes with Hk/MG and high-k capping film to control the eWF. It has been shown that a low long channel Vth is easily achievable with anneal sequence optimization. In particular with the help of laser which creates more dipoles for NMOS case with La-based capping. But also...
This paper overviews integration challenges of low-VT gate-first CMOS featuring one metal gate electrode and one host dielectric with Al2O3 and La2O3 cap-dielectrics for pMOS and nMOS respectively. The advantages and disadvantages of employed low EOT low VT enabling technologies are compared with respect to processing simplicity as well as device performance and reliability. The latest state-of-the...
We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by...
We show for the first time that conduction and valence band-edge effective work functions (WF) are achieved simultaneously by one single Dy2O3 capping layer on HfO2 for both nMOS and pMOS with TaCx-based metals. Low Vt's (0.23 and -0.36 V) are obtained without degrading the EOT-JG scalability and hole mobility. A model based on competing intermixes of cap/host dielectric and cap/metal is proposed...
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