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We have experimentally evaluated the effects of the gate line width roughness (LWR) on the electrical characteristics of scaled n-MOSFETs. A larger gate LWR enhances the fluctuation in the subthreshold leakage current in short-channel n-MOSFETs even when the average gate length is maintained. Consequently, suppressing the gate LWR effectively reduces the variability in the threshold voltage of the...
We have demonstrated for the first time that parallel extension implantation tilted along the gate width direction enables to reduce the threshold voltage (Vth) fluctuation in nMOSFETs at high Vd by 15%. We have clarified by direct carrier profiling and 3D simulation that the parallel implantation makes lateral extension edge smooth (less roughness induced by gate LER). Thanks to reduced fluctuation...
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