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An ultra-low leakage junction design concept is proposed for further scaling of cell transistor for logic-compatible 28-nm embedded DRAM (eDRAM). Raised source/drain (RSD) enables to introduce graded junction to short-channel FET in order to reduce junction leakage. Furthermore, the LDD formed by thermal diffusion of dopant from in-situ phosphorus-doped RSD enables to suppress subthreshold leakage...
An aggressive junction design concept is proposed for further scaling of bulk planar CMOS featuring selectively epi-grown raised source/drain extensions (RSDext) in conjunction with high temperature millisecond annealing (MSA) process and carbon co-implantation. The junction design window enlarged by introducing the RSDext enables us to elaborately control slight "intentional" diffusion...
We demonstrated 26 nm gate length CMOSFETs with an aggressively reduced silicide position down to 5 nm from the gate edge realized about one decade of order junction leakage reduction, and 10% Ion improvement for both N and PFET. Carbon cluster co-implanted raised source/drain extension (SDE) structure, that enables to enhance SDE boron concentration at the silicide interface and to reduce deep halo...
An aggressive junction design concept is proposed for further scaling of bulk CMOS featuring selective epi-growth raised source/drain extentions (RSDext) in conjunction with high temperature millisecond annealing (MSA) process. The junction design window enlarged by introducing the RSDext enables us to perform elaborate control of slight ldquointentionalrdquo diffusion onto the MSA process rather...
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