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Neural networks (NNs) implemented at the transistor level are powerful adaptive systems. They can perform hundreds of operations in parallel but at the expense of a large number of building blocks. In the case of analog realization, an extremely low chip area and low power dissipation can be achieved. To accomplish this, the building blocks should be simple. This brief presents a new current-mode...
This paper presents a digital, transistor level implemented neo-fuzzy neural network. This type of neural network is particularly well suited for real-time applications like those encountered in signal processing and nonlinear system identification. We consider in detail a flexible reconfigurable circuit of a single nonlinear synapse of this network. When combining such circuits, single-layer or multilayer...
This paper presents experimental results demonstrating a positive effect of using conscience mechanism in on chip learning Kohonen networks. Application of this mechanism allows to eliminate so called ldquodead neuronsrdquo, which do not take part in the competition during the learning phase, thus increasing the quantization error of the network. Both Matlab simulations and measurement results are...
In this study, we present a hardware implementation of the conscience mechanism in Kohonen self-organizing maps. The proposed realization of the conscience mechanism is important to the functioning of the neural network as it eliminates so-called dead (inactive) neurons. As a result the network learning, the level quantization error can be reduced. The conscience mechanism and the Winner Take All...
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