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Achieving constant high efficiency is important in adaptive power amplifier design. This paper highlights the achievement of constant efficiency across wide power levels for power amplifiers with tuned drain supply while having a fixed load impedance network. Due to the non-linear behavior of the trans-conductance at lower drain voltage, class AB bias scheme is implemented. Constant efficiency of...
In this paper, a 1 MHz to 3.4 GHz, 5 W, highly linear power amplifier based on GaN HEMT is reported. Load-pull technique has been applied to introduce a compromising solution for the PA performance trade-off problem. Over the whole bandwidth a measured small signal gain of 14 plusmn 0.7 dB and an output return loss of better than -10 dB have been achieved. The input return loss was better than -10...
In this work electromagnetic analysis and experimental verification of integrated microstrip transmission lines on silicon substrates have been performed up to 90 GHz. Several microstrip lines of different width and length have been realized on a five metal layer silicon substrate together with a commercial SiGe HBT process. All structures have been analyzed using a 2.5D electromagnetic simulation...
Special ultra-low-power wakeup receivers have been postulated repeatedly throughout publications in the sensor network community. This paper presents a fully integrated zero-bias detector in BiCMOS technology, which can be used for construction of a wakeup-receiver with -50 dBm sensitivity at a standby current consumption in the order of 100 nA. Operating frequency examined here was 2.4 GHz, but the...
This work presents an active downconverter targeted for integration in 60 GHz high speed data communication RF front-ends. The designed downconverter has been realized in 0.25 mum SiGe BiCMOS technology with ft around 200 GHz. The downconverter consists of a single balanced mixer with an on-chip balun for differential to single ended conversion. High linearity and bandwidth are the main design goals...
This work demonstrates the design of a wideband low noise amplifier in 0.13 um CMOS technology. Important design aspects and the influence of bandwidth improving circuit elements on various LNA performance parameters like gain, matching, noise figure, and stability are analyzed. Simulated and measured LNA results are presented. At the centre frequency of 5.5 GHz the measured LNA performance includes...
The emergence of digital mobile broadband communication systems for voice, data, multimedia and positioning is coupled to the continuous progress of silicon CMOS-technology. Single chip integration with digital part, high integration density, low power consumption, low cost under mass production aspects and excellent RF performance are the current system design challenges. This paper focuses on design...
This work describes a lumped element based MIM capacitor model for the frequency range up to 110 GHz. Several MIM capacitors with different areas have been fabricated in a five metal layer 0.25 m SiGe HBT technology. All structures have been analyzed in a 2.5 D EM simulation environment and the simulated results are compared to measurements. A lumped element model valid up to 110 GHz has been developed...
A complete low power 24 GHz transceiver chain intended for wireless sensor networks is presented. Including standard button cell batteries, the node size is only 1cm3. A specially designed PCB antenna is implemented, which is fed through the substrate from the backside. The RF components are flip chip mounted directly to the feedline to reduce losses. Data transmission at 2400 bps has been demonstrated,...
This paper reviews realization concepts and achievements of wireless sensor nodes and focuses on new developments in the 24 GHz frequency range. The higher frequency offers the advantage of ultra miniaturization and therefore opens new application fields. On the other hand power consumption of the RF-front-end becomes still more challenging than at lower frequencies. It is shown that by applying very...
A wideband amplifier up to 50 GHz has been implemented in a 0.25 žm, 200 GHz ft SiGe BiCMOS technology. Die size was 0.7×0.73 mm2. The two-stage design achieves more than 11 dB gain over the whole 20 to 50 GHz band. Gain maximum was 14.2 dB at 47.5 GHz. Noise figure was lower than 9 dB up to 34 GHz and a current of 30 mA was drawn from a 4 V supply. To the author's best knowledge this is the highest...
A simple method for the implementation of cyclo-stationary shot-noise sources in harmonic balance simulators is proposed. The presented implementation method is particularly useful for the noise analysis in mixers or switching circuits with large signal excitations.
An energy efficient K-band GaAs-HBT amplifier applicable in a highly integrated direct receiver concept for sensor networks is presented. The preamplifier in a direct receiver is the most important building block and mainly determines sensitivity and energy consumption. Special issues of the amplifier design related to the receiver concept are highlighted in this paper. The presented amplifier shows...
This work presents a fully integrated 6 GHz LNA designed using 0.12 mum IBM CMOS technology. The amplifier consumes only 3.6 mW dc power with 1.2 V supply voltage, and features a 11 dB power gain and 3.6 dB noise figure at the frequency of 6 GHz. Additionally, it achieves -11 dBm of input referred 1 dB compression point and -0.5 dBm of IIP3. At the same time input and output matching are better than...
In this paper, the paper presents a low-power mixer with integrated local oscillator intended for use in a 24 GHz receiver front-end. The chip is realized using HBT GaAs technology. The voltage-controlled oscillator (VCO) provides a tuning range of 18% at a mean frequency of 21 GHz, with a low DC consumption of 21 mW. DC consumption of the mixer part is about 17 mW from a 3 V supply, with a mean gain...
This paper shows a fully integrated, ESD protected, low-power, low-voltage amplifier designed with a low-cost 0.18 mum SiGe technology. The amplifier achieves 11 dB gain, 8 dB noise figure at 23 GHz and 1 dB compression point of -18 dBm consuming 2.8 mW from the 0.7 V supply voltage. At this frequency the amplifier shows also 9 and 13 dB input and output return losses, respectively. Gain and power...
A low power 24 GHz signal generator consisting of a 12 GHz VCO and a frequency doubler in GaAs HBT technology is presented. Overall power consumption is 43 mW at 0 dBm output power, tuning range is 800 MHz for 3 V tuning voltage. The doubler by itself provides 3 dB gain at 13 mW power consumption. Its design is based on harmonic termination of an HBT producing the desired harmonic frequency
A wideband amplifier up to 50 GHz has been implemented in a 0.25 mum, 200 GHz ft SiGe BiCMOS technology. Die size was 0.7 times 0.73 mm2. The two-stage design achieves more than 11 dB gain over the whole 20 to 50 GHz band. Gain maximum was 14.2 dB at 47.5 GHz. Noise Figure was lower than 9 dB up to 34 GHz and a current of 30 mA was drawn from a 4 V supply. To the author's best knowledge this is the...
A 22 GHz low-noise amplifier (LNA) was designed, fabricated in standard 0.12 μm CMOS technology and measured. The LNA chip achieves a maximum gain of 5.5 dB, a noise figure of 10.3 dB and return losses at in-/output of 15 and 10 dB, respectively. The LNA operates at a supply voltage 1.2 V and consumes a DC-power of just 5.4 mW. To the author best knowledge it is the first cascode implementation in...
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