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This paper presents the superior electron and hole mobility on a single orientation Ge substrate for compact and cost-effective CMOS applications. The different scattering mechanisms of electron and hole mobility are discussed for understanding carrier transport physics. On the basis of this understanding, the highest electron mobility of 437 cm2/Vs and hole mobility of 213 cm2/Vs at Ns=1e13 cm−2...
We have investigated carrier transport properties in ultra-thin body (UTB) Ge-on-Insulator (GeOI) MOSFETs for the first time. Both n- and p-channel MOSFET operation fabricated on 9 nm GeOI has been demonstrated. In addition, a significant difference of Ge crystallinity in the front-channel from that in back-one is reported to explain the mobility degradation in UTB region.
We have systematically investigated Ge interface passivation methods, and the highest electron (1920 cm2/Vs) and hole mobility (725 cm2/Vs) have been demonstrated by dramatic reduction of Dit through the collaboration of self-passivation and valency passivation. In Si passivation, it is found that Si contributes to the upper half (worse) and lower one (better) in the bandgap differently. This study...
A new model to understand the origin of the dipole formed at high-k/SiO2 interface is presented. In our model, the areal density difference of oxygen atoms at high-k/SiO2 interface is considered as the cause of the dipole. On the basis of our model it is possible to predict the dipole direction and its magnitude for the candidate gate dielectrics, including ones so far not experimentally reported...
Reliabilities of high-k stacked gate dielectrics are discussed from the viewpoint of the impact of initial traps in high-k layer. TDDB reliability can be explained by the generated subordinate carrier injection (GSCI) model. While initial traps increase the leakage current, they do not degrade the TDDB reliability. In contrast, the BTI reliability is strongly degraded by initial traps.
We have demonstrated very high-k (k~50) HfO2 films for ultra-scaled CMOS application. Higher symmetric crystalline structure enables us to achieve higher-k HfO2. We present a feasible method to obtain sub-nm EOT with very high-k HfO2 under actual process conditions, together with an underlying mechanism.
We have investigated effects of the oxygen doping into TaCx on the effective work function (Phim,eff) in TaCx/SiO2/Si and TaCx/HfO2/Si gate stacks. It has been found for the first time that the threshold voltage (Vth) is tunable within 0.5~0.6V for HfO2 MOSFETs by adjusting the oxygen content within 0~12 at. % in TaCx. Furthermore, it has been shown that unknown oxygen content in TaCx gates is a possible...
Advanced CMOS engineering strongly requires materials science-based technology in addition to (rather than) demonstrating exotic non-planar device structures and/or various smart integration techniques. This paper describes typical examples of materials-related device engineering in metal gate/high-k CMOS developments, focusing on basic issues such as EOT scalability with higher-k, an inversion layer...
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