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In this paper, we present a distributed arithmetic (DA) formulation of the computation of discrete wavelet transform (DWT) using 9/7 filters, and mapped that into bit-parallel and bit-serial architectures for high-throughput and low-hardware implementations, respectively. The bit-serial structure processes the bit-slices of input vector in serial manner for low-hardware solution, while the bit-parallel...
In this paper, we propose a data-access scheme for transposition-free implementation of separable 2-D finite impulse response (FIR) filters for finite input matrix. The functionality of 2-D FIR filter based on the proposed data-access technique has been validated through MATLAB simulation. A pipelined architecture is derived further for hardware-efficient high-throughput implementation of this filter...
Fully-pipelined simple modular structures are presented in this paper for efficient hardware realization of discrete Hadamard transform (HT). From the kernel matrix of HT, we have derived four different pipelined modular designs for transform length N = 4. It is shown further that the HT of transform-length N = 8 can be obtained from two 4-point HT modules, and similarly, the HT of transform-length...
In this paper, we present a novel fully-pipelined bit-serial architecture for systolic implementation of non-separable two-dimensional discrete wavelet transform (2-D DWT). The computations which become redundant due to the decimation process are eliminated to obtain an efficient computing algorithm for the 2-D DWT. Moreover, the critical path is reduced in the proposed design to have a small bit-level...
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