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In this paper, we present a distributed arithmetic (DA) formulation of the computation of discrete wavelet transform (DWT) using 9/7 filters, and mapped that into bit-parallel and bit-serial architectures for high-throughput and low-hardware implementations, respectively. The bit-serial structure processes the bit-slices of input vector in serial manner for low-hardware solution, while the bit-parallel...
In this paper, we have presented a bit-serial systolic-like architecture for the computation of non-separable two-dimensional discrete wavelet transform (2-D DWT) based on the principle of distributed arithmetic. The computational core of the proposed structure is highly regular and modular. The computations which become redundant due to the decimation process are eliminated to obtain a low-complexity...
In this paper, we propose a pipelined-architecture for high-throughput computation of multilevel lifting 2D discrete wavelet transform (DWT). The multilevel DWT computation is shared by the proposed devices based on pyramid algorithm (PA) and recursive pyramid algorithm (RPA), where the PA-based devices compute the lower order subands and the higher order subbands are computed by an RPA-based device...
In this paper, we propose a pipeline architecture for VLSI implementation of multilevel lifting-based discrete wavelet transform (DWT). The proposed architecture can compute multilevel lifting DWT of an TV-point data-sequence in N/2 clock cycles. For implementing the TV -point DWT using (5, 3) filters the proposed structure requires two more multipliers and four more adders compared with the corresponding...
In this paper, we present a fully pipelined and modular array architecture for reduced-latency high-speed implementation of discrete wavelet transform (DWT). The efficiency of the structure is improved in the proposed design by implementing the computation for the first level decomposition by pyramid algorithm and higher level decomposition by recursive pyramid algorithm in the same processing modules...
In this paper, we present a novel systolic implementation of separable two-dimensional (2-D) discrete wavelet transform (DWT). Unlike the existing structures, the proposed design does not require any input/output network or additional hardware unit for transposition of intermediate output matrix. Consequently, it provides a significant saving of hardware and computation-time. It has 100% hardware...
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