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This paper reports a single-chip full-band 3.1 10.6GHz ESD UWB LNA featuring cascode shunt-series feedback topology and very robust whole-chip ESD protection. Careful ESD+LNA co-design was excised to achieve full-chip circuit optimization with high ESD protection. This design is implemented in a foundry 0.18μm RFCMOS process. Measurement shows the highest reported ESD protection of 8.25kV, a peak...
Analog-to-digital conversion plays an essential role in all kinds of electronics systems, including signal processing, communications and storage. In particular, interpolated flash ADC has been widely used in high-speed systems requiring very high sampling speed. Obviously, practical ADC design is very challenging, which has been dominated by experiences and trial-and-error skills. This is true to...
A new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters (ADC) is presented. The new offset averaging design technique takes full advantages of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance...
A new ESD-sensitive LNA design method is presented, featuring S-parameter modelling and input matching network re-matching techniques for ESD+LNA full-chip design optimization. Design of 5 GHz LNA with 5 kV ESD protection in a 0.18 mum RFCMOS technology shows ESD-induced performance reduction in gain and noise figure up to -14.3% and +18% over a 1.8 GHz bandwidth range, which can be recovered by +76...
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