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Due to the high integration on vertical stacked layers, power/ground network design becomes one of the critical challenges in 3D IC design. With the leakage-thermal dependency, the increasing on-chip temperature in 3D designs has serious impact on IR drop due to the increased wire resistance and increased leakage current. Power/ground (P/G) TSVs can help to relieve the IR drop violation by vertically...
The three-dimensional (3D) integration circuit is a new technology with higher integration density and better performance than 2D ICs. To solve the critical thermal issue in 3D layout, we propose a force-directed floorplanning algorithm. This algorithm naturally integrates with the planning of thermal vias and reasonably allocates white space for inserting the thermal vias. It solves the problem of...
Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous approaches still have a significant weakness. That is, they usually construct a gated clock tree after cell placement, i.e., cell placement is performed without considering clock gating and may generate a solution unfriendly to subsequent...
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