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This paper presents a new physics-based method for reliability prediction and modeling of Integrated Circuits (ICs). By implementing transistor degradation mechanisms via differential equations in the transistor compact model, the aging of the circuit can be simulated over (accelerated) time under real conditions. Actually, each transistor in the circuit integrates the voltage, current and temperature...
In semiconductor industry, designing a SoC is a complex process. Designing reliable SoCs includes study of various configurations involving different operating conditions and considering both hard and soft errors. Designers at higher level of abstraction already have many ways to remove or handle soft errors. This paper aims at analyzing hard errors at functional level. We propose a methodology using...
With the increase in the design complexity of MPSoC architectures, estimating power consumption is very complex and time consuming at lower level of abstraction. We propose a methodology using ArchC named Power-ArchC for a fast high-level estimation of processor power consumption. Power values are obtained by an instruction level power characterization at gate level. The requirements for power evaluation...
In this paper the modeling results of a given InP/InGaAs/InP DHBT technology (0.7 × 7 μm emitter area) have been shown with two advanced compact models, HICUM L0 and Agilent HBT. Shortcomings of these models have been pointed out and their suitability for modeling these high frequency devices has been discussed.
The lifetime of integrated chip tends to decrease more and more with technology scaling. To check if a design is robust, in this paper we present RTME (real time MTTF evaluation), a simulation framework that enables the evaluation of reliability at higher level of abstraction layer. Using the output of RTME, we are able to distinguish the effect of different benchmarks on different blocks of the processor.
This paper presents an original method of analog circuits aging simulation. This method is based on a behavioral modelling of circuits that includes the effects of degradations on circuit parameters, on the basis of transistors aging. The efficiency of the method is demonstrated in the case of hot carriers degradation in an amplifier
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