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The breakdown (TDDB/SILC) characteristics of nMOS transistors with hafnium-based gate dielectric stacks of various zirconium content were investigated. It is found that the gate stack composition affects the SILC-voltage dependency while the voltage value chosen for SILC monitoring impacts significantly the SILC-based lifetime projection. For the worst case lifetime evaluation, SILC should be monitored...
La-doped HfSiO samples show lower threshold voltage (Vth) and gate current (Igate), which is attributed to dipole formation at the high-k/SiO2 interface. At low and intermediate field stress, La-doped devices exhibit better immunity to positive bias temperature instability (PBTI) due to their lower charge trapping efficiency than the control HfSiO, which mainly results from a dipole-induced greater...
To understand hot carrier effects on high-k dielectrics without cold carrier trapping, we have investigated hot carrier induced damage with channel and substrate hot carrier stresses. Comparing substrate hot carrier stress, channel hot carrier stress showed significant cold carrier injection during hot carrier injection. Using a relaxation bias, we are able to evaluate hot carrier induced permanent...
Constant voltage stress (CVS) combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO2 /HfO2/TiN stacks. Using the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps, we have determined that the voltage stress-induced generation of the defects contributing to threshold voltage instability in high-k gate stacks...
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