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In this paper, a novel device architecture, namely novel self-align double gate MOSFET with source/drain tie, is proposed and compared with the ITRS. According to the simulation results, our proposed transistor not only enhances the on/off current ratio, but also decreases the drain induced barrier lowering and subthreshold swing due to the double gate scheme structure.
This paper aims to investigate the performance and reliability trade-off of the self-aligned (SA) pi-shaped source/drain (S/D) ultrathin silicon-on-insulator (UTSOI) field-effect transistors (FETs). Based on the simulations, the S/D-tie effects are crucial to the future of quasi-SOI devices. The preliminary results of electrical characteristics of the SA-piFETs are carefully demonstrated.
This paper is to investigate the novel features of a Local Oxidation of silicon multi-tie body polycrystalline silicon thin-film transistor (LOCOS MTB poly-Si TFT) by using numerical simulations. Based on the results, our proposed TFT have improved reliability due to the presence of the LOCOS MTB scheme. Although a multi-body-tied scheme is not compatible in current TFT process, it is believed that...
We present a new vertical sidewall MOSFET with embedded gate (EGVMOS) to reduce the parasitic capacitance which is the major disadvantage in a conventional VMOS. According to simulations, our EGVMOS can not only achieve about 86.34% and 54.76% reduction at Cgd at VDs = 0.05 V and 1.0 V respectively, but also improves the device reliability due to suppressed kink effects, in comparison with a conventional...
In this paper, we propose a novel self-aligned silicon-on-insulator (SOI) MOSFET with Omega-shaped conductive layer and source/drain-tie (SA-OmegaCFET). Based on the TCAD 2D simulation results, we find that combining the applications of a nature Source/Drain (S/D) tie with a recessed S/D region can effectively improve the issue of self-heating effects, but without losing control of the short-channel...
In this work, we present a novel vertical MOSFET with embedded gate structure and try to overcome the challenges mentioned above by modifying the junction depth. Therefore, four types of vertical sidewall MOSFETs with embedded gate (EVGMOS) are also demonstrated and called the EVGMOS having lightly-doped drain (LDD) w/o or w/ 2.5 nm Si etching after gate formation and non-LDD w/o or w/ 2.5 nm Si etching...
In this study, we propose a novel polysilicon thin-film transistor with multi-trenched body (MTB TFT). According to the ISE-TCAD simulations, our proposed MTB TFT gets a steep subthreshold swing (S.S.), a reduced drain-induced barrier lowering (DIBL), a lower drain off-state leakage, and a higher ION/IOFF ration, in comparison with a conventional poly-Si TFT. In addition, due to the MTB scheme, the...
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