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In this paper, we propose a novel unipolar CMOS device with embedded oxide. Good inverter and logic gate output waveforms and behaviors are obtained. Utilizing the punch through effect, the Non-Classical Unipolar CMOS is demonstrated to enhance the tPLH so that the average delay time can be improved 23% when compared with the conventional CMOS. Due to all NMOS structures are only exploited and the...
This paper presents a non-conventional CMOS device, which is composed of an nMOSFET and a tunneling field effect transistor (TFET) for driver and load. Based on the measurement data of TFET device published, we have for the first time drawn the Q line of the new designed CMOS compared with the conventional CMOS to verify its feasibility. The static power consumption of it can be optimized and reduced...
In this paper, for the first time, we demonstrate the radio frequency (RF) performance of a junctionless vertical MOSFET (JLVMOS). According to the numerical simulation results, the JLVMOS can obtain higher gm, lower gd, in comparison to a junctionless planar SOI MOSFET. This because the vertical double-gate (DG) scheme truly helps to increase the gate controllability over the channel region, resulting...
We present a non-traditional CMOS inverter composed a junctionless (JL) NMOSFET and an N+-N--P transistor which with simple process and high integration density in this paper. In the non-traditional CMOS inverter the JL NMOSFET serves as driver and the N+-N--P transistor serves as load, respectively. Based on the measurement date of the N+-N--P transistor published, we draw the load line of the non-traditional...
In this study, junctionless technology employed for fabricating pseudo tri-gate vertical (PTGV) MOSFETs is proposed and the RF/analog performance is also investigated and demonstrated. According to simulation results, the excellent performances such as high transconductance (gm), high cut-off frequency (fτ), and high transconductance generation factor (gm/Id) arc achieved. The numerical results also...
This paper proposes a novel vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM application. The bMPI 1T-DRAM can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved about 95% when compared to the planer bMPI 1T-DRAM. Because of the double gate structure, the proposed device has...
A new STI-type FinFET structure with its body region been connected is demonstrated and characterized by using three-dimensional (3-D) numerical simulations. From the simulation results, the STI-type FinFET shows that the short-channel effects (SCEs) and the off-state leakage current are proved to be reduced because the threshold voltage (VTH) roll-off and the drain-induced barrier lowering (DIBL)...
In this paper, we propose a simple trench-oxide thin-film transistor (TO TFT) process for 1T-DRAM applications. Our proposed TO TFT structure has several novel features as follows: 1. The buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process. 2. The trench design is used to improve both the sensing current windows (~72%) and the retention...
In this study, we propose a novel bulkSi-based device called dual-channel body-tied (DCBT) MOSFET using the self-aligned process without any extra masks. It reveals that our proposed DCBT FET has excellent S.S., decreased Isd,leak, lower Rsd, reduced Jg,limit, smaller lattice temperature, and higher thermal stability when compared with its DC counterpart. And, for the first time, we will investigate...
This study presents a new vertical MOSFET with recessed gate (RG). Based on the TCAD simulation results, our proposed VMOS structure can gain reduced parasitic capacitance (compared to the conventional VMOS, both Cgd and Cgs can be reduced about 12% and 38.78%, respectively at VDs =1.0 V), improved drain saturation current, and free kink characteristics, in comparison to a conventional VMOS structure...
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