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This paper reports a self-temperature compensating barometer, which effectively avoided the influence of the surrounding temperature on device performance without extra temperature sensors. The micro sensor in the barometer was based on resonant mechanism. Two doubly-clamped resonators with identical sizes were fabricated on a pressure-sensitive membrane, which have reversed response to the applied...
This paper first investigates the mechanism of the temperature effects on characteristics of MEMS based electrochemical seismic sensors for linear motion detecting both by numerical simulation and experimental methods. Both the simulation and experimental results indicates that the device sensitivity increases with temperature and the tendency of the device frequency response remains the same under...
High density through-silicon-via (TSV) and cost-effective 3D die-to-wafer integration scheme are proposed as best-in-class foundry solutions for high-end CMOS chips at 28 nm node and beyond. Key processes include: TSV formation, extreme thinning of the TSV wafer and die-to-wafer assembly. The impact of extreme thinning on device threshold voltage, leakage currents, and Ion-Ioff characteristics of...
Electroluminescence devices based on nanocrystalline Si/SiO2 multilayers were fabricated and the luminescence can be observed both from vertical and lateral direction. Moreover, P-doped nanocrystalline Si/SiO2 multilayers were prepared and the improved electro-luminescence characteristics were achieved.
Integration of high-k/metal gate stacks has been discussed in this paper. Pre-gate clean, interfacial oxide treatment, high-k and metal film deposition were investigated for optimized Jg-EOT. Various approaches such as HF vapor clean, surface hydroxylation treatment, and metal gate modification (such as interface treatment and high density top layer) were employed to improve the electrical properties...
The concept of diffusion topography engineering (DTE) is proposed and exercised on state-of-the-art 65 nm technology for the first time. Diffusion region extended over STI and therefore resulting in T-shape diffusion profile is created purposely to suppress STI stress and oxide divot. This novel technique delivers up to 33% PMOS and 22% NMOS enhancement, respectively, and results in -10% R.O. speed...
A new CMOS ISFET readout circuit is presented in this paper. The interface circuits is based on VI converter like design plus a grounded ISFET device biased in the triode region together with a source follower in a self-biasing configuration. The major advantage of this design is the elimination of body effect in the ISFET sensing element, thus reducing extra temperature dependent effect on modulating...
In the ballast circuit, the piezoelectric transformer is used to replace the conventional inductor-capacitor resonant tank saving valuable space and cost. In the past, design of the piezoelectric transformer (PT) or Transonerreg for the ballast circuit has been difficult due to the complex interaction between the physical and electrical equivalent circuit characteristics. Previous ballast design using...
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