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High density through-silicon-via (TSV) and cost-effective 3D die-to-wafer integration scheme are proposed as best-in-class foundry solutions for high-end CMOS chips at 28 nm node and beyond. Key processes include: TSV formation, extreme thinning of the TSV wafer and die-to-wafer assembly. The impact of extreme thinning on device threshold voltage, leakage currents, and Ion-Ioff characteristics of...
Integration of high-k/metal gate stacks has been discussed in this paper. Pre-gate clean, interfacial oxide treatment, high-k and metal film deposition were investigated for optimized Jg-EOT. Various approaches such as HF vapor clean, surface hydroxylation treatment, and metal gate modification (such as interface treatment and high density top layer) were employed to improve the electrical properties...
The concept of diffusion topography engineering (DTE) is proposed and exercised on state-of-the-art 65 nm technology for the first time. Diffusion region extended over STI and therefore resulting in T-shape diffusion profile is created purposely to suppress STI stress and oxide divot. This novel technique delivers up to 33% PMOS and 22% NMOS enhancement, respectively, and results in -10% R.O. speed...
A new CMOS ISFET readout circuit is presented in this paper. The interface circuits is based on VI converter like design plus a grounded ISFET device biased in the triode region together with a source follower in a self-biasing configuration. The major advantage of this design is the elimination of body effect in the ISFET sensing element, thus reducing extra temperature dependent effect on modulating...
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