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Notice of Violation of IEEE Publication Principles??Spur and Noise Reduction Techniques in Ring Oscillator Based Frequency Synthesizers for Broadcast Receiver SoCs??by Maxim, A.in the IEEE Radio and Wireless Symposium, January 2008.After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.Specifically, the paper contains references...
Notice of Violation of IEEE Publication Principles??Single and Dual Loop Ring Oscillator Based Frequency Synthesizers for Broadband Tuner Applications??by A. Maxim,in the Proceedings of the Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE3-5 June 2007 Page(s):225 - 228After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication...
Notice of Violation of IEEE Publication Principles"A -5OdBc Spur 0.13 μm CMOS Ring Oscillator PLL for DBS Satellite Receiver SOCs Using a Multi-Regulator Architecture"by Maxim, A.; Poorfard, R.; Kao, J.;in the Proceedings of the 2007 IEEE Radio and Wireless Symposium,Jan. 2007 Page(s):427-430After careful and considered review, it has been determined that the above paper is in violation...
Notice of Violation of IEEE Publication Principles"A -85dBc Reference Spurs Quadratude 1-2.5GHz Dual-Path Sampled Loop Filter CMOS PLL with sub-1??rms Phase Noise"by Maxim, A.; Gheorghe, M.;in the 2006 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. San Francisco, CA, 2006After careful and considered review, it has been determined that the above paper is in violation of IEEE's...
This paper presents a multigigahertz active clock deskewing architecture that uses analog phase interpolation to replace the area-consuming capacitively controlled delay lines used in regional clock deskewing delay-locked loops. It provides a small phase step that is uniform and process-independent over the entire 2/spl pi/ phase deskew range, which reduces the intra-die clock skew. The phase interpolators...
Notice of Violation of IEEE Publication Principles??A 2-5GHz low jitter 0.13 ??m CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application]??by Maxim, A.in the Proceedings of the IEEE 2004 Custom Integrated Circuits Conference,3-6 Oct. 2004 Page(s): 147 - 150After careful and considered review, it has been determined that the above...
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