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A novel NOR Flash cell with a build-in 2-bit capability consisting of two physically isolated ONO charge-storage nodes separated by an oxide dielectric in between over the channel region is demonstrated. This memory cell employs the virtual ground array architecture, much like NROM arrays, is sensed with the reverse read scheme. However, comparing to NROM, this novel cell offers a wider Vt window...
Post gate-etch reoxidation in plasma H2/O2 was successfully employed to non-volatile TANOS charge-trap memory devices without any adverse oxidation on the TaN gate-electrode sidewall. Using this plasma reoxidation process showed significant device improvement in the narrow gate retention and endurance characteristics. This improvement is thought to result from gate etch damage repair, and locally...
We demonstrate best in class performance for MANOS-type charge-trap flash non-volatile memory devices through improved program/erase (P/E), endurance and retention. Band-engineered (BE) tunnel-oxides (TO) and BE-SiNx charge-trap layers are employed to optimize program, erase, and endurance with trade-off in retention. However, for the 1st time we combine BE-TO, BE-SiNx, BE-blocking layer (BE-BL) and...
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