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Application of IDDQ testing to LSIs fabricated using advanced process technology is becoming increasingly difficult due to large variability of scaled devices. In this paper, we propose a novel technique that adaptively determines per-chip current-threshold for IDDQ testing to enhance test accuracy. In the proposed technique, process condition of a chip and fault-sensitization vector are first estimated...
Post-fabrication performance compensation and adaptive delay testing are effective means to improve yield and reliability of LSIs. In these methods, process parameter estimation plays a key role. In this paper, we propose a novel technique for accurate on-chip process parameter estimation. The proposed technique is based on Bayes' theorem, in which on-chip parameters, such as threshold voltages, are...
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