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In this paper, a programmable precise time delay generator suitable for a beam forming impulse ground penetrating radar (GPR) is presented. The design is based on a phase locked loop (PLL) circuit that is implemented utilizing Global Foundries 7HV 0.18μm CMOS process. The precise time control realizes the true time delay, which allows for developing an ultrawide band (UWB) phased array GPR system...
We present a new method of performing high-resolution path delay testing on designs targeted to field-programmable gate arrays. Our built-in self-test (BIST) architecture uses an on-chip delay line element to set the launch time of each test pattern generator to its optimum point for stressing paths in the routed chip. The rising and falling edges of each test pattern are controllable with high precision,...
In this paper, the authors focus on modeling the data dependent jitter (DDJ) in high-speed interconnect. To investigate the data dependent jitter, the analysis is performed with Fourier series based on the interconnect RLC model. By calculating the pattern dependent delay deviation, the data dependent jitter is characterized. To validate the modeling accuracy, the analysis results have been compared...
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