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Controller synthesis uses hardware description language and synthesis optimization tools from a higher abstract level. State transition graph of completely specified finite state machine is adopted to describe the behavior of controller. State transition graph STG_org was generated before synthesized and state transition graph STG_ext was reversely extracted from structure realization of controller...
The paper presents an inclusion relation which is used to verify the process of controller synthesis based on incompletely specified finite state machine model. State transition graph is adopted to describe the behavior of controller. State transition graph STG_org was abstract behavior description of controller synthesis generated before synthesized and state transition graph STGext was reversely...
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