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Higher noise tolerance, lower power consumption, and higher reliability are the major design metrics for designing an SRAM cell. It is difficult to achieve an SRAM cell with stable operation at low voltage for low power consumption due to increasing variations in process, voltage, and temperature. It is proved that conventional 6 T fails to maintain its stability in scaled technology, particularly...
At present day SRAM cell is under renewal stage. Researchers are aiming to get an SRAM cell which is reliable and robust against process, voltage and temperature (PVT) fluctuations. An SRAM cell is also expected to support low-power applications. This article proposes a new way for designing an SRAM cell. The proposed cell functions properly even bellow subthreshold region. Therefore, it can be useful...
This article presents a highly stable single-ended 7T (SE-7T) SRAM cell in subthreshold region. Using Monte-Carlo simulations critical design metrics of proposed SE-7T SRAM cells are estimated. Estimated results are compared with that of conventional 6T SRAM cell. The SE-7T SRAM cell offers 2.71× and 2.71× and 8.42 X improvements in Read Access Time (TRA) and Write Access Time (TWA) for write-1 and...
This article presents a new way for designing a more reliable and variability resilient 9T SRAM cell which is based on DTMOS (dynamic threshold MOS) and CCBB (cell content body bias) technique under subthreshold operation. Critical design metrics of SRAM cells are estimated at subthreshold region and compared with that of conventional 9T SRAM cell. The proposed 9T SRAM cell shows 41.8% (9.5%) lower...
This article presents a variability resilient CNFET based 10T S RAM cell. Critical design metrics of S RAM cells are estimated using Monte-Carlo simulations and compared with that of conventional Si-MOSFET based 10T S RAM cell. The CNFET based SRAM cell offers 3.15× and 1.98× improvements in Read Access Time (TRA) and Write Access Time (TWA) respectively. The proposed bit cell also offers 1.94× and...
This article presents a variability resilient FinFET based 10T SRAM cell. Critical design metrics of SRAM cells are estimated at subthreshold region and compared with that of conventional MOSFET based 10T SRAM cell. The FinFET based SRAM cell offers 2.33× and 1.29× improvements in Read Access Time (TRA) and Write Access Time (TWA) respectively. The proposed bitcell also offers 7.06× and 1.54× improvements...
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