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A voltage controlled tunable resistor (VCTR) with precise control over its resistance value, is reported in this paper. 6T based proposed VCTR design requires only six transistors, which reduces the transistor count as compared to 7T or 10T designs already available in the literature. Compact 6T VCTR design operates in the saturation region with a single control voltage. Presented design also mitigates...
Traditional MOS technology has served the industry for years but now, it has become very difficult to continue Moore's law using Dennard's scaling principles. One of the major reasons which limit the scaling of MOS devices is the dramatic increase in the leakage currents. Thus, researchers are continuously trying to develop new technologies to extend Moore's law beyond 22-nm technology node. One of...
Technology scaling results in reduction of the lateral and vertical dimensions of transistors. The supply voltage (VDD) is scaled down to reduce power dissipation and to maintain device reliability (avoid oxide breakdown). The threshold voltage (Vt) is proportionally scaled down in order to maintain the performance. However, narrow oxide thickness and low Vt result in significant rise in gate leakage...
In this paper, we provide a comparative estimation of the W/L aspect ratio required to obtain a symmetric behavior of n-channel and p-channel MOS devices across ultradeep submicron (UDSM) technology nodes and various supply voltage ranges. This symmetric behavior is in terms of matching propagation delay during the pull-up (pMOS dependent) and pull-down (nMOS dependent) output transitions. To achieve...
This article presents a variability resilient CNFET based 10T S RAM cell. Critical design metrics of S RAM cells are estimated using Monte-Carlo simulations and compared with that of conventional Si-MOSFET based 10T S RAM cell. The CNFET based SRAM cell offers 3.15× and 1.98× improvements in Read Access Time (TRA) and Write Access Time (TWA) respectively. The proposed bit cell also offers 1.94× and...
Subthreshold circuits have emerged as a strong alternative for ultralow power applications. This paper first investigates the output levels of the NAND and NOR gates in subthreshold region of operation and carries out analysis on various design metrics. Analysis mainly consists of estimation of propagation delay (tp) and power-delay product (PDP) as a function of supply voltage. It also performs variability...
Subthreshold logic is an efficient technique to achieve ultralow energy per operation for low-to-medium throughput applications. To improve switching performance, energy/switching, and also the robustness of the subthreshold logic for the implementation of 1-bit static full adder, we propose the use of sub-FinFET (sub-threshold voltage FinFET) transistors. The power, speed and energy evaluation has...
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