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Three-dimensional (3D) on-chip memory stacking has been proposed as a promising solution to the “memory wall” challenge with the benefits of low access latency, high data bandwidth, and low power consumption. The stacked memory tiers leverage through-silicon-vias (TSVs) to communicate with logic tiers, and thus dramatically reduce the access latency and improve the data bandwidth without the constraint...
A low complexity algorithm for post-processing deblocking and implementation with a configurable processor designed by us is presented in this paper. The algorithm is aimed at improving subjective visual effect and reducing the complexity for hardware design. According to the masking effect of human visual system (HVS), the blocking artifacts can be recognized only when the blocking artifacts continually...
H.264/AVC is the latest video coding standard with high compression efficiency. Due to its time-consuming in coding, it cannot meet the real-time application requirements. In this paper, an efficient algorithm was proposed based on 2D-histogram according to the feature of intra-frame prediction. In this algorithm, each macroblock is predicted before coding, and one of the two prediction modes is selected...
H.264/AVC is the latest video coding standard with high compression efficiency. Due to its time-consuming in coding, it cannot meet the real-time application requirements. In this paper, an efficient algorithm was proposed based on 2D-Histogram according to the feature of Intra-frame prediction. In this algorithm, each macroblock is predicted before coding, and one of the two prediction modes is selected...
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