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Achieving effective run-time mapping for Network on Chip (NoC) is a big challenge, particularly since the execution time and arrival order of applications are not known a priori. In this paper, we propose an energy-aware run-time mapping scheme, which consists of region selection algorithm and core mapping algorithm, for homogeneous NoC. The proposed scheme minimizes the energy consumption of the...
The network-on-chip (NoC) design methodology is an important trend for large system-on-chip designs to reduce the bandwidth and power constraints in traditional synchronous bus architectures. In the design of packet-based NoC, the packet-length plays an important role in the NoC throughput, latency, and energy consumption. The appropriate NoC packet-length was selected based on simulation and analysis...
Network-on-Chip (NoC) design methodology is considered as an important trend for large System-on-Chip design because of the bandwidth and power constraints in traditional synchronous bus architecture. In the design of packet-based NoC, packetizing mechanism has great effect on communication performance, area, and energy consumption of NoC. In this paper, we carry out detailed simulation to evaluate...
In this paper, a hierarchical cluster-based irregular topology customization method is proposed for Networks-on-Chip (NoC). This method contains three steps: (1) partitioning IPs into many hierarchical clusters; (2) generating a core network; (3) deleting redundant edge routers. Results show that the irregular topologies generated by our hierarchical cluster-based method consume less power when satisfying...
This paper proposes a method to guarantee bandwidth or latency of network-on-chip. Compared with circuit-switch method, this method can guarantee the latency between one flitpsilas generation and its reception and support a wide range of traffic types. Also, a maximum latency formula is developed. Results show that this method guarantees the bandwidth and latency well and is low-cost.
In this paper, we propose dual-channel access mechanism to design cost-effective NoC based on 2D-mesh topology. Compared with traditional single-channel access mechanism, our scheme greatly increases the throughput and cuts down the average latency with reasonable implementation cost, especially when the traffic load is high.
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