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In this paper, a new delay-locked loop (DLL) architecture is proposed to effectively improve the DLL jitter performance. A novel realignment duty cycle corrector (RDCC) is proposed for the DLL. The RDCC circuit can make the output waveform of the DLL maintain a 50% duty cycle in a lock mode. The RDCC circuit has advantages of low power consumption, small chip area and high operating frequency. The...
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