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A 45 nm CMOS 60 GHz PA optimized for linear modulation with 6 dbm saturated power and 13 dB gain is presented when biased at 70uA/um. A maximum power added efficiency (PAE) of 19.4% 8 dBm Psat and 18 dB gain is achieved for 200 uA/um bias point. The PA was tested using a predistortion algorithm and OFDM packets, and achieved PAE of 6.1% with -28 dB EVM and 9% with -20 dB EVM at output powers of -2...
A 60 GHz 4 element bidirectional phased-array TX/RX chip with a 2 bit phase shifter and IF converter to/from 12 GHz, using 90 nm CMOS process, is described. The array features 7 dB gain, measured noise figure (NF) of 9 dB, IP1dB of -19 dbm for RX, and output Psat of +3.5 dBm for TX , drawing 60 mA from a 1.3-V supply. The RMS amplitude and phase error of the phase shifter is 0.7 dB and 2deg max respectively...
This paper presents a 60 GHz LNA designed in a 90 nm CMOS process with 6 metals Cu thick metal, and Ft/Fmax of 100 GHz/150 GHz demonstrating best known noise figure, gain, power consumption and size compared to earlier 60-GHz LNAs reported. It features 15 dB of gain, a measured noise figure (NF) of 4.4 dB, while drawing 3 mA from a 1.3-V supply. The use of spiral inductors enables a reduction in transistor...
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