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This paper presents an all-digital PMOS and NMOS process variability monitor which utilizes a simple buffer ring with a pulse counter. The proposed circuit monitors the process variability according to a count number of a single pulse which propagates on the buffer ring and a fixed logic level after the pulse vanishes. The proposed circuit has been fabricated in 65nm CMOS process and the measurement...
We have designed and measured the performance against power supply bounce and aging of a Self Synchronous FPGA (SSFPGA) in 65nm CMOS which achieves 2.97GHz throughput at 1.2V. The proposed SSFPGA employs a 38×38 array of 4-input, 3-stage Self Synchronous Configurable Logic Blocks (SSCLB), with the introduction of a new dual tree-divider 4 input LUT to achieve a 4.5× throughput improvement over our...
The performance and robustness to PVT variations has been measured of an improved Self Synchronous FPGA (SSFPGA) designed in 65 nm CMOS which achieves 2.97 GHz throughput at 1.2V. The proposed SSFPGA employs a 38×38 array of 4-input, 3-stage Self Synchronous Configurable Logic Blocks, with the introduction of a new dual tree-divider 4 input LUT to achieve a 4.5× throughput improvement...
The reliable operation against PVT (process, voltage, and temperature) variation and aging effects has been measured of a Gate-Level Pipelined Self Synchronous FPGA (SSFPGA) design in 65nm CMOS. The SSFPGA employs a 38×38 array of 4-input, 3-stage Self Synchronous Configurable Logic blocks. Throughput has been measured at 2.97GHz at 1.2V, with correct operation from 750mV to 1.6V at 25°C. The operation...
This paper presents an all-digital process variability monitor which utilizes a simple buffer ring with a pulse counter. The proposed circuit monitors the process variability according to a count number of a single pulse which propagates on the buffer ring and a fixed logic level after the pulse vanishes. The proposed circuit has been fabricated in 65nm CMOS process and the measurement results demonstrate...
We introduce a 42x cascaded time difference amplifier (TDA) using differencial logic delay cells with 0.18??m CMOS process. By employing differential logic cells for the delay chain instead of CMOS logic cells, our TDA has stable time difference gain (TD gain) and fine time resolution. Measurement results show that our TDA achieves less than 5.5% TD gain offset and ??250ps input range.
A design environment for stripe-shaped PMELA TFTs on glass has been developed and successfully tested. Cell library including standard cells, logic synthesis database, place and route rule, layout parasitic extraction rule and transistor models are developed. Measurement results show that the digital circuits designed in this environment work correctly. They also show that the simulation environment...
This paper presents measurement results on datapath delay distributions for data/instruction against Process, Voltage and Temperature (PVT) variations in 90 nm CMOS. Datapath delay has been measured using a completion signal generated at the end of datapaths with dual-rail logic according to data and instructions comprehensively for multiple Vdd and Temperature among several chips to show PVT variations...
In this paper, a position detection sensor for 3-D measurement is presented. The sensor is designed for detecting positions of laser spots projected on target objects quickly. The sensor has a 256×256 pixel array, a set of address decoders for variable block access and a variable block logical-OR circuit on an 8.9mm × 8.9mm die. The sensor is designed and fabricated in 0.6 µm 3-Metal 2-Poly-Si CMOS...
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