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Phase shifter is an important constituent element of magnonic devices, especially for the operations of logic gates based on spin waves. The mechanisms and ways to control phase shift of propagating spin waves have been studied for a period of time by both experiments and theory. The most universal design of spin-wave phase shifter is to use an Ostered field produced by a highly localized dc current...
We explore the use of oxygen vacancies for nonvolatile data storage by trapping electrons in the high-k, gate dielectric layer of NFETs. Programming is performed via channel carrier injection and is erased by tunneling. 64Kb arrays were constructed and reliability is demonstrated.
A self-aligned approach was developed to fabricate planar gated nanowire field emitter arrays (FEAs). A single mask was used to etch the gate dielectric and define the area for nanowire growth, in which a self-alignment between the gate and the nanowire cathode is achieved. A planar gated ZnO nanowires FEAs was fabricated by using this approach .
In this paper, the reliable SiNx/AlGaN/GaN MISHEMTs on silicon substrate with improved trap-related characteristics have been well demonstrated. The devices with our proposed treatment method showed less deep-level traps and more Si surface donors at SiNx-AlGaN interface. The trap related device characteristics are also improved by using our optimized treatment method. The devices with proposed treatment...
CMOS-compatible GaN-on-silicon technology with excellent D-mode MISHFET performance is realized. A low specific contact resistance Rc (0.35 Ω-mm) is achieved by Au-free process. MIS-HFET with a gate-drain distance (LGD) of 15 μm exhibits a large breakdown voltage (BV) (980 V with grounded substrate) and a low specific on-resistance (R ON,sp) (1.45 mΩ-cm2). The importance of epitaxial quality in a...
A cost competitive 20nm technology node is described that enabled industry-first 20nm cellular modem chip with 2× peak data rates vs 28nm, and 2× carrier aggregation. Process and design enhancements for layout context optimization, and continuous process improvements resulted in 18% boost in circuit performance while simultaneously achieving >30% power reduction. 3 mask local interconnect and 64nm...
Replacement metal gate (RMG) process requires gate fill with low resistance materials on top of work function tuning metals. Conventional titanium (Ti)-aluminum (Al) based RMG metal fill scheme for low resistance gate formation becomes challenging with further gate length scaling for 20nm node and beyond. In this work, we have demonstrated competitive low resistance gate formation at smaller than...
In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive...
This paper summarizes our recent investigations of nano-wire n type tunneling field effect transistor (n-TFET) reliability by experimental measurements and physical analysis [1-3]. Large PBTI and HC degradations which are very different from those in conventional n-MOSFETs were observed. The results are interpreted by different degradation mechanism in TFET.
This paper presents performance evaluation of high-kappa/metal gate (HK/MG) process on an industry standard 45 nm low power microprocessor built on bulk substrate. CMOS devices built with HK/MG demonstrate 50% improvement in NFET and 65% improvement in PFET drive current when compared with industry standard 45 nm Poly/SiON devices. No additional stress elements were used for this performance gain...
This paper describes SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum2 and 0.124 mum2. SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, thanks to HK-MG Tinv scaling. Cell read current is increased by 70% over Poly-SiON process. Ultra dense cell process window is expanded with optimized contact...
For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V Vdd with a low cost process. With this high performance transistor,...
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