The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Performance of triple GEM prototypes has been evaluated by means of a muon beam at the H4 line of the SPS test area at CERN. The data from two planar prototypes have been reconstructed and analyzed offline with two clusterization methods: the center of gravity of the charge distribution and the micro Time Projection Chamber (μTPC). GEM prototype performance evaluation, performed with the analysis...
The NA62 experiment at the CERN-SPS is designed to study the K + → π+νν ultra-rare decay using a high intensity hadron beam and detecting its decay products. The lowest level (Level-0, L0) trigger processor represents a crucial component in reducing the event rate, estimated to be about 10 MHz for most of the sub-detectors which form the trigger, by a factor 10 with a maximum admitted latency of 1...
A commercial Graphics Processing Unit (GPU) is used to build a fast Level 0 (L0) trigger system for the NA62 experiment at CERN. In particular, the parallel computing power of the GPU is exploited to perform real-time fitting in the Ring Imaging CHerenkov (RICH) detector for the L0 trigger of the NA62 experiment. Direct GPU communication using a FPGA-based board has been used to reduce the data transmission...
The paper presents test results of a front-end ASIC developed for fast timing applications with silicon pixel detectors. Implemented in a 0.13 μm CMOS process, the prototype integrates 107 read-out cells. In an area of 300 μm × 300 μm each cell incorporates a fast transimpedance amplifier with 3 ns peaking time, a Constant Fraction Discriminator (CFD) and a Time to Digital Converter (TDC). The analog...
The paper describes the design of a front-end chip for hybrid pixel detectors optimized for good timing resolution (200 ps rms) and high event rate (150 kHz per pixel). Each channel consists of a fast transimpedance amplifier with 5 ns peaking time, a constant fraction discriminator (CFD), and a Time-to-Digital Converter (TDC). In order to cope with the rate requirement, a multi-event buffering scheme...
The authors describe a VLSI processor for pattern recognition based on content addressable memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, searching...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.