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Memory accesses form an important source of timing unpredictability. Timing analysis of real-time embedded software thus requires bounding the time for memory accesses. Multiprocessing, a popular approach for performance enhancement, opens up the opportunity for concurrent execution. However due to contention for any shared memory by different processing cores, memory access behavior becomes more...
With rapid development of communication technology, the signal integrity is impacting the system performance much more than before. So either in the IC design or in the system design, it is very important to investigate negative timing analysis and its mathematical modeling in the high speed integrated circuit. In the paper, we introduce the origin of the negative timing script in the deep sub-micrometer...
We have developed a modified bias-dependent Cannpsilas model and performed IC design and hardware experiments to study the linearization of a highly-efficient monolithic quasi-class E SiGe power amplifier (PA) IC using both envelope-tracking (ET) and Envelope-elimination-and-restoration (EER) techniques. Our simple PA behavior model fits the measured SiGe PA IC data very well across a wide range of...
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