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A novel bulk-Si based pMOSFET structure is presented featuring a high-mobility SiGe0.45 channel and raised SiGe0.25 source/drains. This device offers enhanced scalability with respect to standard pMOS devices, leading to 50% improved drive current. 30nm gate length devices show a high drive current of ~580 μA/μm for IOFF=100nA/μm, DIBL=126mV/V, SS=80mV/dec, showing superior electro- statics without...
We explore the limits of sub-melt laser annealing on blanket SiGe/Si-cap layers with Ge concentrations up to 55% using High-Resolution X-ray Diffraction (HR-XRD) and a new non-contact metrology to measure the mobility of inversion charges. We discuss the influence of the laser peak temperature and SiGe/Si stack parameters. It is shown that for high Ge concentrations and SiGe/Si-cap thicknesses of...
We have studied n+ Si:C stressor formation by C or C7H7 ion implantation on blanket wafers for different integration schemes (so-called post Source/Drain versus post Source/Drain Extension integration). Using sheet resistance and High Resolution X-Ray Diffraction (HR-XRD) fitting parameters as the main metrics, we studied the influence of different implant/anneal parameters as well as the process...
We demonstrate electrically functional 0.099 μm2 6T-SRAM cells using full-field EUV lithography for contact and M1 levels. This enables formation of dense arrays without requiring any OPC/RET, while exhibiting substantial process latitudes & potential lower cost of ownership (single-patterning). Key enablers include: 1) high-k/metal gate FinFETs with Lg˜40 nm, 12-17 nm wide Fins, and cell β ratio...
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